Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide, is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate electrode is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form source and drain regions. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day semiconductor microelectronic fabrication processes form features having less than 0.25 critical dimensions, for example in future processes even less than 0.13 microns. As feature size decreases, the size of the resulting transistor as well as transistor features also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single die area.
In semiconductor microelectronic device fabrication, polysilicon and silicon dioxide (SiO2) are commonly used to respectively form gate electrodes and gate dielectrics for metal-oxide-semiconductor (MOS) transistors. As device dimensions have continued to scale down, the thickness of the SiO2 gate dielectric layer has also decreased to maintain the same capacitance between the gate and channel regions. A thickness of the gate oxide layer of less than 2 nanometers (nm) will be required to meet smaller device design constraints. A problem with using SiO2 as the gate dielectric is that thin SiO2 oxide films may break down when subjected to electric fields expected in some operating environments, particularly for gate oxides less than about 50 Angstroms thick. In addition, electrons more readily pass through an insulating gate dielectric as it gets thinner due to what is frequently referred to as the quantum mechanical tunneling effect. In this manner, a tunneling current, produces a leakage current passing through the gate dielectric between the semiconductor substrate and the gate electrode, increasingly adversely affecting the operability of the device.
Because of high direct tunneling currents, SiO2 films thinner than 1.5 nm cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts to replace SiO2 with high-k (high dielectric constant) dielectrics, including for example, TiO2, Ta2O5, ZrO2, Y2O3, La2O5, HfO2, and their aluminates and silicates attracting the greatest attention. A higher dielectric constant gate dielectric allows a thicker gate dielectric to be formed which dramatically reduces tunneling current and consequently gate leakage current, thereby overcoming a severe limitation in the use of SiO2 as the gate dielectric. While silicon dioxide (SiO2) has a dielectric constant of approximately 4, other candidate high-k dielectrics have significantly higher dielectric constant values of, for example, 20 or more. Using a high-k material for a gate dielectric allows a high capacitance to be achieved even with a relatively thick dielectric. Typical candidate high-k dielectric gate oxide materials have high dielectric constant in the range of about 20 to 40.
There have been, however, difficulties in removing or etching certain high-k dielectric materials, particularly, oxides of hafnium and zirconium, for example hafnium dioxide and zirconium dioxide. Chemical etchants used with high-k materials may cause damage to associated oxide materials making high temperature rapid thermal oxidation (RTO) processes necessary to repair such damage which in turn may adversely affect the crystallinity or level of defects at the gate dielectric/silicon or silicon dioxide interface thereby degrading electrical performance. For example, typically a shallow trench isolation (STI) electrical isolation structure is formed adjacent a CMOS structure to electrically isolate the various CMOS devices. A high-k dielectric layer is formed over the silicon substrate including the STI trench which has been previous backfilled with SiO2. In a subsequent etching step to remove a portion of the high-k gate dielectric surrounding the gate structure to reveal the silicon substrate, for example to form a metal silicide layer, a high selectivity of etching of the high-k gate dielectric to SiO2 is required to avoid etching the STI oxide which tends to form etching divots at the STI trench corner regions thereby degrading electrical isolation performance. In addition, high-k dielectrics such as oxides of zirconium and hafnium are increasingly advantageously used as etching stop layers due to their etching resistance. Prior art processes for removing oxides of hafnium and zirconium have use sulfuric acid heated to temperatures of between about 150° C. and about 180° C. The selectivity in the etching rate of the oxides of hafnium and zirconium, for example hafnium dioxide (HfO2) and zirconium dioxide (ZrO2), with respect to SiO2, is about 0.6 to about 1 with an etching rate of about 1 Angstrom/min. As a result, etching rates and selectivity to underlying SiO2 layers for etching of oxides of hafnium and zirconium is not optimal, successful etching operations optimally requiring higher etching rates and selectivity with respect to SiO2 thereby allowing reduced processing times and larger processing windows without the formation of etching divots. In addition, the added cost of implementing adequate environmental and safety protective measures for handling hot sulfuric acid as well as providing acid resistant processing tools is undesirable.
For example referring to FIG. 1A is shown a cross sectional view of a portion of a CMOS semiconductor device showing a STI trench 12A formed in silicon substrate 10 and backfilled with STI oxide 12B. Overlying the STI oxide is a high-k dielectric material layer 14, for example hafnium dioxide or zirconium dioxide, formed for forming a gate dielectric in a CMOS device in an adjacent gate structure (not shown). Referring to FIG. 1B according to prior art methods of etching the high-k dielectric material layer, using, for example hot sulfuric acid, etching divots e.g., 16A and 16B are formed at the STI trench corner regions degrading device electrical isolation.
Therefore it would be advantageous to the semiconductor micro-fabrication processing art to develop a lower cost and more effective wet etching composition and method for etching high-k materials including oxides of hafnium and zirconium.
It is therefore an object of the invention to provide a lower cost and more effective wet etching composition and method for etching high-k materials including oxides of hafnium and zirconium while overcoming other shortcomings and deficiencies of the prior art.